The present invention relates to a method of manufacturing high-density integrated semiconductor devices such as MOS transistors and CMOS devices formed in or on a semiconductor wafer substrate and having low resistance, ultra-shallow junctions forming low junction leakage source and drain regions by utilizing self-aligned, refractory metal suicide (xe2x80x9csalicidexe2x80x9d) processing. The invention has particular utility in contact formation or local interconnect formation processes.
The escalating requirements for high-density and performance associated with ultra-large scale integration semiconductor devices necessitate design rules of 0.18 xcexcm and below, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features, e.g., of source, drain, and gate regions of transistors formed in or on a common semiconductor substrate, challenges the limitations of conventional junction and contact formation technology, including photolithographic, etching, and deposition techniques.
As a result of the ever increasing demand for large-scale and ultra-small dimension integrated semiconductor devices, self-aligned techniques have become the preferred technology for forming such devices in view of their simplicity and capability of high-density integration. As device dimensions decrease, both vertically and laterally, many problems arise, especially those caused by an increase in sheet resistance of the contact areas to the source and drain regions and junction leakage as junction layer thickness decreases. To overcome this problem, the use of highly electrically conductive refractory metal silicides has become commonplace in the manufacture of integrated semiconductor devices comprising, e.g., MOS type transistors. Another technique employed in conjunction with refractory metal silicide technology is the use of lightly doped drains (xe2x80x9cLDDsxe2x80x9d). An LDD consists of a lightly doped source/drain region (i.e., dopant densities on the order of about 9xc3x971019 da/cm3) formed just at the edge of the gate region, while a more heavily doped drain region (i.e., dopant densities on the order of about 2xc3x971020 da/cm3), to which ohmic contact is to be provided, is laterally displaced away from the gate by provision of a sidewall spacer on the gate electrode.
Salicide processing involves deposition of a metal that forms an intermetallic compound with silicon, but does not react with silicon oxides or silicon nitrides during normal processing conditions.
Refractory metals commonly employed in salicide processing include titanium, nickel, and cobalt, each of which forms very low resistivity phases with silicon, e.g., TsSi2, NiSi and CoSi2. In practice, the refractory metal is deposited in a uniform thickness over all exposed surface features of the silicon wafer, preferably by means of physical vapor deposition (PVD) from an ultra-pure sputtering target and an ultrahigh vacuum, multi-chamber DC magnetron sputtering system. In MOS transistor formation, deposition is generally performed both after gate etch and after source/drain junction formation. After deposition, the refractory metal blankets the polysilicon gate electrode, the silicon oxide or nitride spacers, the silicon oxide isolation regions, and the exposed portions of the source and drain regions. As a result of a rapid thermal annealing (RTA) process performed in an inert atmosphere, the refractory metal reacts with underlying polysilicon and silicon to form electrically conductive silicide layer portions on the top surface of the gate electrode and on the exposed portions of the source and drain regions. Unreacted portions of the refractory metal, e.g., on the silicon oxide or silicon nitride sidewall spacers and the silicon oxide isolation regions, are then removed. This may be done by a wet etch process which is selective to the metal silicide portions. In some instances, e.g., with cobalt, a first RTA step may be performed at a relatively low temperature from about 400xc2x0 C. to about 550xc2x0 C. for 20 sec to 120 sec in order to form first-phase CoSi which is then subjected to a second RTA step performed at a relatively high temperature from about 700xc2x0 C. to about 850xc2x0 C. for from about 20 sec to about 60 sec to convert the CoSi to second-phase, lower resistivity CoSi2. The second RTA step is performed after selective etch of the non-reacted cobalt.
Taking advantage of the increasing number of devices provided by ultra-large scale integration and the continued shrinking of the device and circuit features requires formation of the devices into one or more circuits, necessitating the interconnection of these various devices. To accomplish interconnection on such a small scale, a local interconnect is typically used within an integrated circuit to provide an electrical connection between two or more conducting or semiconducting regions (e.g., active regions of one or more devices). For example, a plurallity of transistors can be connected to form an inverting logical circuit using local interconnects.
The local interconnect is typically a relatively low resistance material, such as a conductor or doped semiconductor, that is formed to electrically couple the selected regions. For example, in certain arrangements, damascene techniques are used to provide local interconnects made of tungsten (W), or a like conductor, which is deposited within an etched opening, such as a via or a trench that connects the selected regions. The use of local interconnects reduces the coupling burden on the subsequently formed higher layers to provide such connectivity, which reduces the overall circuit size and as such tends to increase the circuit""s performance.
The combination of the salicidation process and the local interconnect formation process creates certain difficulties. In particular, the etching of an interlayerer dielectric (ILD) to form the via or trench in which the local interconnects are formed often overetches the LDD sidewall spacers on the sidewalls of the gate. This is due to the preferential attacking of the spacer material (such as an oxide) that comprises the sidewall spacers. This is known as xe2x80x9cgougingxe2x80x9d of the device junctions. This gouging leads to undesirable sidewall profiles and possibly can produce shorts.
There is a need for a method of forming an electrical connection, such as a contact or a local interconnect, that does not gouge device junctions during the etching process caused by preferential etching of the spacers.
This and other needs are met by the present invention which provides a method of forming an electrical connection to a semiconductor device comprising the steps of forming a gate on a substrate, this gate having a top surface and sidewalls. A layer of spacer material is deposited over the substrate and the gate. The layer of spacer material is etched to form sidewall spacers on the sidewalls of the gate. This etching is performed so that portions of the gate sidewalls are free of spacer material and other portions of the gate sidewalls are covered by the sidewall spacers. A silicide is formed on the semiconductor device. The silicide is formed on the top surface and those portions of the gate sidewalls that are free of spacer material.
The deliberate etching of the spacer material to expose portions of the gate sidewalls during the formation of the sidewall spacers allows the silicide to be formed on the gate sidewalls. During the subsequent local interconnect or contact etch, the spacer and an LDD oxide will not be preferentially attacked during a contact etch or a local interconnect etch. This prevents the gouging of the device junctions and undesirable profiles or possible shorts.
The earlier stated needs are also met by another embodiment of the present invention which provides an arrangement comprising a substrate and a gate on the substrate, with the gate having sidewalls and a top surface. Active regions are formed in the substrate. Sidewall spacers cover a portion of the gate sidewalls. Silicide regions are on the active regions, the gate top surface and the gate sidewalls.
An advantage of the arrangement of the present invention is the presence of silicide regions on the gate sidewalls that serve to prevent the preferential attacking of the sidewall spacers that cover the remaining portions of the gate sidewalls. Hence, during local interconnect or contact etch, neither the LDD oxide nor the sidewall spacers are preferentially attacked and the desirable profiles of the spacer is maintained and possible shorts are prevented.
In another embodiment of the present invention, a method of preventing gouging of device junctions during the formation of an electrical connection to the device junctions is provided. This method comprises the steps of forming a spacer layer over a semiconductor device having active regions and a gate with a top surface and sidewalls. The spacer layer is etched to form sidewall spacers. The step includes overetching the sidewall spacers to remove the sidewall spacers from portions of the gate sidewalls. Silicide regions are formed on the active regions, the gate top surface and the gate sidewalls.
An advantage of the method of the present invention is the relative ease of preventing the gouging that may occur during the contact etch or local interconnect etch. The present invention achieves this without adding a process step by continuing the etching to the spacer layer to overetch the sidewall spacers. Hence, a separate step of etching to remove the sidewall spacers from portions of the gate sidewalls is not required according to embodiments of the present invention. At the same time, however, the overetching of the sidewall spacers allows silicide regions to be formed on the gate sidewalls, which then prevent the LDD oxide and the sidewall spacers from being preferentially attacked during the contact etch or local interconnect etch.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.